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<div class="title">xcresample_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaed484ae65a37d6caf256fb3583b3f869"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaed484ae65a37d6caf256fb3583b3f869">XCRESAMPLE_HW_H_</a></td></tr>
<tr class="memdesc:gaed484ae65a37d6caf256fb3583b3f869"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__cresample__v4__0.html#gaed484ae65a37d6caf256fb3583b3f869">More...</a><br /></td></tr>
<tr class="separator:gaed484ae65a37d6caf256fb3583b3f869"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2fabb0e08576485f3f54cd1f4531024a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga2fabb0e08576485f3f54cd1f4531024a">XCRE_ACTIVE_SIZE_OFFSET</a>&#160;&#160;&#160;0x0020</td></tr>
<tr class="memdesc:ga2fabb0e08576485f3f54cd1f4531024a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal and vertical active frame size.  <a href="group__cresample__v4__0.html#ga2fabb0e08576485f3f54cd1f4531024a">More...</a><br /></td></tr>
<tr class="separator:ga2fabb0e08576485f3f54cd1f4531024a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b1a96d8791a35a4cbb98d7be3f27b5a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga0b1a96d8791a35a4cbb98d7be3f27b5a">XCRE_ENCODING_OFFSET</a>&#160;&#160;&#160;0x0028</td></tr>
<tr class="memdesc:ga0b1a96d8791a35a4cbb98d7be3f27b5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frame encoding.  <a href="group__cresample__v4__0.html#ga0b1a96d8791a35a4cbb98d7be3f27b5a">More...</a><br /></td></tr>
<tr class="separator:ga0b1a96d8791a35a4cbb98d7be3f27b5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab08648fa4329ccb2f1f792c049d0d96e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gab08648fa4329ccb2f1f792c049d0d96e">XCRE_COEF00_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0100</td></tr>
<tr class="memdesc:gab08648fa4329ccb2f1f792c049d0d96e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 00 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gab08648fa4329ccb2f1f792c049d0d96e">More...</a><br /></td></tr>
<tr class="separator:gab08648fa4329ccb2f1f792c049d0d96e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf45ea16c39ab86263617c9f72733a5ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf45ea16c39ab86263617c9f72733a5ec">XCRE_COEF01_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0104</td></tr>
<tr class="memdesc:gaf45ea16c39ab86263617c9f72733a5ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 01 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaf45ea16c39ab86263617c9f72733a5ec">More...</a><br /></td></tr>
<tr class="separator:gaf45ea16c39ab86263617c9f72733a5ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1c4e8aa886cb44126fb45f54d4d2561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gae1c4e8aa886cb44126fb45f54d4d2561">XCRE_COEF02_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0108</td></tr>
<tr class="memdesc:gae1c4e8aa886cb44126fb45f54d4d2561"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 02 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gae1c4e8aa886cb44126fb45f54d4d2561">More...</a><br /></td></tr>
<tr class="separator:gae1c4e8aa886cb44126fb45f54d4d2561"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa661ff07f1c20ab1839c9a85fca60571"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaa661ff07f1c20ab1839c9a85fca60571">XCRE_COEF03_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x010C</td></tr>
<tr class="memdesc:gaa661ff07f1c20ab1839c9a85fca60571"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 03 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaa661ff07f1c20ab1839c9a85fca60571">More...</a><br /></td></tr>
<tr class="separator:gaa661ff07f1c20ab1839c9a85fca60571"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdc160496035e2d1c64e1f6855356681"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gafdc160496035e2d1c64e1f6855356681">XCRE_COEF04_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0110</td></tr>
<tr class="memdesc:gafdc160496035e2d1c64e1f6855356681"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 04 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gafdc160496035e2d1c64e1f6855356681">More...</a><br /></td></tr>
<tr class="separator:gafdc160496035e2d1c64e1f6855356681"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02e0f97aa30b4805922757f17e0b12cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga02e0f97aa30b4805922757f17e0b12cd">XCRE_COEF05_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0114</td></tr>
<tr class="memdesc:ga02e0f97aa30b4805922757f17e0b12cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 05 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga02e0f97aa30b4805922757f17e0b12cd">More...</a><br /></td></tr>
<tr class="separator:ga02e0f97aa30b4805922757f17e0b12cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a56ac84b8403ceece66d68623c3a091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga9a56ac84b8403ceece66d68623c3a091">XCRE_COEF06_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0118</td></tr>
<tr class="memdesc:ga9a56ac84b8403ceece66d68623c3a091"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 06 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga9a56ac84b8403ceece66d68623c3a091">More...</a><br /></td></tr>
<tr class="separator:ga9a56ac84b8403ceece66d68623c3a091"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95a23cf13a13e9186541d1aaaae78966"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga95a23cf13a13e9186541d1aaaae78966">XCRE_COEF07_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x011C</td></tr>
<tr class="memdesc:ga95a23cf13a13e9186541d1aaaae78966"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 07 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga95a23cf13a13e9186541d1aaaae78966">More...</a><br /></td></tr>
<tr class="separator:ga95a23cf13a13e9186541d1aaaae78966"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06bd5b0189a2bfc254383e64e1b1ba70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga06bd5b0189a2bfc254383e64e1b1ba70">XCRE_COEF08_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0120</td></tr>
<tr class="memdesc:ga06bd5b0189a2bfc254383e64e1b1ba70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 08 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga06bd5b0189a2bfc254383e64e1b1ba70">More...</a><br /></td></tr>
<tr class="separator:ga06bd5b0189a2bfc254383e64e1b1ba70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45c917cbe5b9acdc47758738a71d08f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga45c917cbe5b9acdc47758738a71d08f9">XCRE_COEF09_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0124</td></tr>
<tr class="memdesc:ga45c917cbe5b9acdc47758738a71d08f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 09 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga45c917cbe5b9acdc47758738a71d08f9">More...</a><br /></td></tr>
<tr class="separator:ga45c917cbe5b9acdc47758738a71d08f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga327a4b079f7630c0efc499590035d2f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga327a4b079f7630c0efc499590035d2f5">XCRE_COEF10_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0128</td></tr>
<tr class="memdesc:ga327a4b079f7630c0efc499590035d2f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 10 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga327a4b079f7630c0efc499590035d2f5">More...</a><br /></td></tr>
<tr class="separator:ga327a4b079f7630c0efc499590035d2f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ccae86cacb8f7938a000ef7b2b340b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga7ccae86cacb8f7938a000ef7b2b340b3">XCRE_COEF11_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x012C</td></tr>
<tr class="memdesc:ga7ccae86cacb8f7938a000ef7b2b340b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 11 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga7ccae86cacb8f7938a000ef7b2b340b3">More...</a><br /></td></tr>
<tr class="separator:ga7ccae86cacb8f7938a000ef7b2b340b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadd607ad747e8eced4dfa42c24f1b210"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaadd607ad747e8eced4dfa42c24f1b210">XCRE_COEF12_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0130</td></tr>
<tr class="memdesc:gaadd607ad747e8eced4dfa42c24f1b210"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 12 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaadd607ad747e8eced4dfa42c24f1b210">More...</a><br /></td></tr>
<tr class="separator:gaadd607ad747e8eced4dfa42c24f1b210"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14577474f7d7dea3726b0bd3bdcaaa8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga14577474f7d7dea3726b0bd3bdcaaa8a">XCRE_COEF13_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0134</td></tr>
<tr class="memdesc:ga14577474f7d7dea3726b0bd3bdcaaa8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 13 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga14577474f7d7dea3726b0bd3bdcaaa8a">More...</a><br /></td></tr>
<tr class="separator:ga14577474f7d7dea3726b0bd3bdcaaa8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeaf0e4311f3cec9a4dbfd4d0223d0bfd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaeaf0e4311f3cec9a4dbfd4d0223d0bfd">XCRE_COEF14_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0138</td></tr>
<tr class="memdesc:gaeaf0e4311f3cec9a4dbfd4d0223d0bfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 14 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaeaf0e4311f3cec9a4dbfd4d0223d0bfd">More...</a><br /></td></tr>
<tr class="separator:gaeaf0e4311f3cec9a4dbfd4d0223d0bfd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac849fad3963b4ccdb4df399ce89a0676"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gac849fad3963b4ccdb4df399ce89a0676">XCRE_COEF15_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x013C</td></tr>
<tr class="memdesc:gac849fad3963b4ccdb4df399ce89a0676"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 15 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gac849fad3963b4ccdb4df399ce89a0676">More...</a><br /></td></tr>
<tr class="separator:gac849fad3963b4ccdb4df399ce89a0676"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed4c2f3e422cff8544d123b1f6c7d65d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaed4c2f3e422cff8544d123b1f6c7d65d">XCRE_COEF16_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0140</td></tr>
<tr class="memdesc:gaed4c2f3e422cff8544d123b1f6c7d65d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 16 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaed4c2f3e422cff8544d123b1f6c7d65d">More...</a><br /></td></tr>
<tr class="separator:gaed4c2f3e422cff8544d123b1f6c7d65d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6ed3d2863457dc989f43b7a30be104c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf6ed3d2863457dc989f43b7a30be104c">XCRE_COEF17_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0144</td></tr>
<tr class="memdesc:gaf6ed3d2863457dc989f43b7a30be104c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 17 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaf6ed3d2863457dc989f43b7a30be104c">More...</a><br /></td></tr>
<tr class="separator:gaf6ed3d2863457dc989f43b7a30be104c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga046c61c31ee39d736055df51e19e2938"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga046c61c31ee39d736055df51e19e2938">XCRE_COEF18_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0148</td></tr>
<tr class="memdesc:ga046c61c31ee39d736055df51e19e2938"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 18 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga046c61c31ee39d736055df51e19e2938">More...</a><br /></td></tr>
<tr class="separator:ga046c61c31ee39d736055df51e19e2938"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga106e8fddab9ff751602884fbd58f9332"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga106e8fddab9ff751602884fbd58f9332">XCRE_COEF19_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x014C</td></tr>
<tr class="memdesc:ga106e8fddab9ff751602884fbd58f9332"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 19 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga106e8fddab9ff751602884fbd58f9332">More...</a><br /></td></tr>
<tr class="separator:ga106e8fddab9ff751602884fbd58f9332"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98e024bc3a1c98c73e7858fcba25d8bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga98e024bc3a1c98c73e7858fcba25d8bb">XCRE_COEF20_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0150</td></tr>
<tr class="memdesc:ga98e024bc3a1c98c73e7858fcba25d8bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 20 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga98e024bc3a1c98c73e7858fcba25d8bb">More...</a><br /></td></tr>
<tr class="separator:ga98e024bc3a1c98c73e7858fcba25d8bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f9df4d920cc235338a1acd1f452ba8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga0f9df4d920cc235338a1acd1f452ba8b">XCRE_COEF21_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0154</td></tr>
<tr class="memdesc:ga0f9df4d920cc235338a1acd1f452ba8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 21 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga0f9df4d920cc235338a1acd1f452ba8b">More...</a><br /></td></tr>
<tr class="separator:ga0f9df4d920cc235338a1acd1f452ba8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf80e94e18e368f0120b46986f9dfdad9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf80e94e18e368f0120b46986f9dfdad9">XCRE_COEF22_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x0158</td></tr>
<tr class="memdesc:gaf80e94e18e368f0120b46986f9dfdad9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 22 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#gaf80e94e18e368f0120b46986f9dfdad9">More...</a><br /></td></tr>
<tr class="separator:gaf80e94e18e368f0120b46986f9dfdad9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga43f073717f0cd43bf75b3f51f927307f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga43f073717f0cd43bf75b3f51f927307f">XCRE_COEF23_HPHASE0_OFFSET</a>&#160;&#160;&#160;0x015C</td></tr>
<tr class="memdesc:ga43f073717f0cd43bf75b3f51f927307f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 23 of horizontal phase 0 filter.  <a href="group__cresample__v4__0.html#ga43f073717f0cd43bf75b3f51f927307f">More...</a><br /></td></tr>
<tr class="separator:ga43f073717f0cd43bf75b3f51f927307f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ad7438e92fb57b98c26f50645a9575f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga1ad7438e92fb57b98c26f50645a9575f">XCRE_COEF00_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0160</td></tr>
<tr class="memdesc:ga1ad7438e92fb57b98c26f50645a9575f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 00 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga1ad7438e92fb57b98c26f50645a9575f">More...</a><br /></td></tr>
<tr class="separator:ga1ad7438e92fb57b98c26f50645a9575f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f48d6fb21b46e73c7af5a0b9c01e155"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga8f48d6fb21b46e73c7af5a0b9c01e155">XCRE_COEF01_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0164</td></tr>
<tr class="memdesc:ga8f48d6fb21b46e73c7af5a0b9c01e155"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 01 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga8f48d6fb21b46e73c7af5a0b9c01e155">More...</a><br /></td></tr>
<tr class="separator:ga8f48d6fb21b46e73c7af5a0b9c01e155"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafaf168f142154b67616c59cf9827becb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gafaf168f142154b67616c59cf9827becb">XCRE_COEF02_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0168</td></tr>
<tr class="memdesc:gafaf168f142154b67616c59cf9827becb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 02 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gafaf168f142154b67616c59cf9827becb">More...</a><br /></td></tr>
<tr class="separator:gafaf168f142154b67616c59cf9827becb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga34b5d6d0f4bb4d418788b19e5bda0a72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga34b5d6d0f4bb4d418788b19e5bda0a72">XCRE_COEF03_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x016C</td></tr>
<tr class="memdesc:ga34b5d6d0f4bb4d418788b19e5bda0a72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 03 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga34b5d6d0f4bb4d418788b19e5bda0a72">More...</a><br /></td></tr>
<tr class="separator:ga34b5d6d0f4bb4d418788b19e5bda0a72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d7be6ce93a5d3f38132fff3a3993398"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga9d7be6ce93a5d3f38132fff3a3993398">XCRE_COEF04_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0170</td></tr>
<tr class="memdesc:ga9d7be6ce93a5d3f38132fff3a3993398"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 04 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga9d7be6ce93a5d3f38132fff3a3993398">More...</a><br /></td></tr>
<tr class="separator:ga9d7be6ce93a5d3f38132fff3a3993398"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac9a0d2f1f791b58c0318170c9ff19c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaac9a0d2f1f791b58c0318170c9ff19c1">XCRE_COEF05_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0174</td></tr>
<tr class="memdesc:gaac9a0d2f1f791b58c0318170c9ff19c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 05 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaac9a0d2f1f791b58c0318170c9ff19c1">More...</a><br /></td></tr>
<tr class="separator:gaac9a0d2f1f791b58c0318170c9ff19c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabde07b24b8a06faaa6afea4babf96cb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gabde07b24b8a06faaa6afea4babf96cb4">XCRE_COEF06_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0178</td></tr>
<tr class="memdesc:gabde07b24b8a06faaa6afea4babf96cb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 06 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gabde07b24b8a06faaa6afea4babf96cb4">More...</a><br /></td></tr>
<tr class="separator:gabde07b24b8a06faaa6afea4babf96cb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga39f483d811bfae7e47a81bcba344bc5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga39f483d811bfae7e47a81bcba344bc5d">XCRE_COEF07_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x017C</td></tr>
<tr class="memdesc:ga39f483d811bfae7e47a81bcba344bc5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 07 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga39f483d811bfae7e47a81bcba344bc5d">More...</a><br /></td></tr>
<tr class="separator:ga39f483d811bfae7e47a81bcba344bc5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab810d46329c8e8f94477fac3928f7bfe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gab810d46329c8e8f94477fac3928f7bfe">XCRE_COEF08_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0180</td></tr>
<tr class="memdesc:gab810d46329c8e8f94477fac3928f7bfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 08 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gab810d46329c8e8f94477fac3928f7bfe">More...</a><br /></td></tr>
<tr class="separator:gab810d46329c8e8f94477fac3928f7bfe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf66dbe711e5a3bd1287fa19424151734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf66dbe711e5a3bd1287fa19424151734">XCRE_COEF09_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0184</td></tr>
<tr class="memdesc:gaf66dbe711e5a3bd1287fa19424151734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 09 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaf66dbe711e5a3bd1287fa19424151734">More...</a><br /></td></tr>
<tr class="separator:gaf66dbe711e5a3bd1287fa19424151734"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3981c2527addc4d02d56f31fd29672ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga3981c2527addc4d02d56f31fd29672ff">XCRE_COEF10_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0188</td></tr>
<tr class="memdesc:ga3981c2527addc4d02d56f31fd29672ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 10 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga3981c2527addc4d02d56f31fd29672ff">More...</a><br /></td></tr>
<tr class="separator:ga3981c2527addc4d02d56f31fd29672ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad22ec3304706b2f7bd65477092dcc48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaad22ec3304706b2f7bd65477092dcc48">XCRE_COEF11_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x018C</td></tr>
<tr class="memdesc:gaad22ec3304706b2f7bd65477092dcc48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 11 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaad22ec3304706b2f7bd65477092dcc48">More...</a><br /></td></tr>
<tr class="separator:gaad22ec3304706b2f7bd65477092dcc48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3a93fd8d3b70b689aef9cb68b186dcb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gab3a93fd8d3b70b689aef9cb68b186dcb">XCRE_COEF12_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0190</td></tr>
<tr class="memdesc:gab3a93fd8d3b70b689aef9cb68b186dcb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 12 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gab3a93fd8d3b70b689aef9cb68b186dcb">More...</a><br /></td></tr>
<tr class="separator:gab3a93fd8d3b70b689aef9cb68b186dcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7658dbc810aa4b13f63121f26dc44ab2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga7658dbc810aa4b13f63121f26dc44ab2">XCRE_COEF13_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0194</td></tr>
<tr class="memdesc:ga7658dbc810aa4b13f63121f26dc44ab2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 13 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga7658dbc810aa4b13f63121f26dc44ab2">More...</a><br /></td></tr>
<tr class="separator:ga7658dbc810aa4b13f63121f26dc44ab2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae79641e31df71116fc605d5386a18df2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gae79641e31df71116fc605d5386a18df2">XCRE_COEF14_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x0198</td></tr>
<tr class="memdesc:gae79641e31df71116fc605d5386a18df2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 14 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gae79641e31df71116fc605d5386a18df2">More...</a><br /></td></tr>
<tr class="separator:gae79641e31df71116fc605d5386a18df2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c62d9914671287c36bf1da711dc391d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga0c62d9914671287c36bf1da711dc391d">XCRE_COEF15_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x019C</td></tr>
<tr class="memdesc:ga0c62d9914671287c36bf1da711dc391d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 15 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga0c62d9914671287c36bf1da711dc391d">More...</a><br /></td></tr>
<tr class="separator:ga0c62d9914671287c36bf1da711dc391d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b47a1512cdb344615d915c6a453e882"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga3b47a1512cdb344615d915c6a453e882">XCRE_COEF16_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01A0</td></tr>
<tr class="memdesc:ga3b47a1512cdb344615d915c6a453e882"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 16 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga3b47a1512cdb344615d915c6a453e882">More...</a><br /></td></tr>
<tr class="separator:ga3b47a1512cdb344615d915c6a453e882"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa62506d1e68b6f634d343a485b8f3fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaaa62506d1e68b6f634d343a485b8f3fd">XCRE_COEF17_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01A4</td></tr>
<tr class="memdesc:gaaa62506d1e68b6f634d343a485b8f3fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 17 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaaa62506d1e68b6f634d343a485b8f3fd">More...</a><br /></td></tr>
<tr class="separator:gaaa62506d1e68b6f634d343a485b8f3fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga801129c4f1f57a1ab118bc0e51bd9bf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga801129c4f1f57a1ab118bc0e51bd9bf4">XCRE_COEF18_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01A8</td></tr>
<tr class="memdesc:ga801129c4f1f57a1ab118bc0e51bd9bf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 18 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga801129c4f1f57a1ab118bc0e51bd9bf4">More...</a><br /></td></tr>
<tr class="separator:ga801129c4f1f57a1ab118bc0e51bd9bf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96f0a8dded48e008b0661bd45dffe388"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga96f0a8dded48e008b0661bd45dffe388">XCRE_COEF19_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01AC</td></tr>
<tr class="memdesc:ga96f0a8dded48e008b0661bd45dffe388"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 19 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga96f0a8dded48e008b0661bd45dffe388">More...</a><br /></td></tr>
<tr class="separator:ga96f0a8dded48e008b0661bd45dffe388"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf7cb29773e11a645b50a551279a5bf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gacf7cb29773e11a645b50a551279a5bf5">XCRE_COEF20_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01B0</td></tr>
<tr class="memdesc:gacf7cb29773e11a645b50a551279a5bf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 20 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gacf7cb29773e11a645b50a551279a5bf5">More...</a><br /></td></tr>
<tr class="separator:gacf7cb29773e11a645b50a551279a5bf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa49389e2a7506c092f1e21fc34001360"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaa49389e2a7506c092f1e21fc34001360">XCRE_COEF21_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01B4</td></tr>
<tr class="memdesc:gaa49389e2a7506c092f1e21fc34001360"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 21 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaa49389e2a7506c092f1e21fc34001360">More...</a><br /></td></tr>
<tr class="separator:gaa49389e2a7506c092f1e21fc34001360"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7270ab4cf94edeed371f32494e8c99d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga7270ab4cf94edeed371f32494e8c99d7">XCRE_COEF22_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01B8</td></tr>
<tr class="memdesc:ga7270ab4cf94edeed371f32494e8c99d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 22 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#ga7270ab4cf94edeed371f32494e8c99d7">More...</a><br /></td></tr>
<tr class="separator:ga7270ab4cf94edeed371f32494e8c99d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae4cbb76dfe9b462d729aea1f24b172c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaae4cbb76dfe9b462d729aea1f24b172c">XCRE_COEF23_HPHASE1_OFFSET</a>&#160;&#160;&#160;0x01BC</td></tr>
<tr class="memdesc:gaae4cbb76dfe9b462d729aea1f24b172c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 23 of horizontal phase 1 filter.  <a href="group__cresample__v4__0.html#gaae4cbb76dfe9b462d729aea1f24b172c">More...</a><br /></td></tr>
<tr class="separator:gaae4cbb76dfe9b462d729aea1f24b172c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c618712800d861c59fb9deefd45a2b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga7c618712800d861c59fb9deefd45a2b6">XCRE_COEF00_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01C0</td></tr>
<tr class="memdesc:ga7c618712800d861c59fb9deefd45a2b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 00 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#ga7c618712800d861c59fb9deefd45a2b6">More...</a><br /></td></tr>
<tr class="separator:ga7c618712800d861c59fb9deefd45a2b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac06a91cdd2b2a82b72724082d82b42b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaac06a91cdd2b2a82b72724082d82b42b">XCRE_COEF01_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01C4</td></tr>
<tr class="memdesc:gaac06a91cdd2b2a82b72724082d82b42b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 01 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#gaac06a91cdd2b2a82b72724082d82b42b">More...</a><br /></td></tr>
<tr class="separator:gaac06a91cdd2b2a82b72724082d82b42b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae68fe139eec3456e8436d45d375f93fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gae68fe139eec3456e8436d45d375f93fb">XCRE_COEF02_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01C8</td></tr>
<tr class="memdesc:gae68fe139eec3456e8436d45d375f93fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 02 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#gae68fe139eec3456e8436d45d375f93fb">More...</a><br /></td></tr>
<tr class="separator:gae68fe139eec3456e8436d45d375f93fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61fe2e129ee73467a333bde971a09ab1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga61fe2e129ee73467a333bde971a09ab1">XCRE_COEF03_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01CC</td></tr>
<tr class="memdesc:ga61fe2e129ee73467a333bde971a09ab1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 03 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#ga61fe2e129ee73467a333bde971a09ab1">More...</a><br /></td></tr>
<tr class="separator:ga61fe2e129ee73467a333bde971a09ab1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga960e2dce62f01924ee5a8082ba5a77f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga960e2dce62f01924ee5a8082ba5a77f2">XCRE_COEF04_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01D0</td></tr>
<tr class="memdesc:ga960e2dce62f01924ee5a8082ba5a77f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 04 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#ga960e2dce62f01924ee5a8082ba5a77f2">More...</a><br /></td></tr>
<tr class="separator:ga960e2dce62f01924ee5a8082ba5a77f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7adb9cc708f775c981b14d40fe66f017"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga7adb9cc708f775c981b14d40fe66f017">XCRE_COEF05_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01D4</td></tr>
<tr class="memdesc:ga7adb9cc708f775c981b14d40fe66f017"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 05 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#ga7adb9cc708f775c981b14d40fe66f017">More...</a><br /></td></tr>
<tr class="separator:ga7adb9cc708f775c981b14d40fe66f017"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabbeced8c7f115327ee61a961cfa80b72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gabbeced8c7f115327ee61a961cfa80b72">XCRE_COEF06_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01D8</td></tr>
<tr class="memdesc:gabbeced8c7f115327ee61a961cfa80b72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 06 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#gabbeced8c7f115327ee61a961cfa80b72">More...</a><br /></td></tr>
<tr class="separator:gabbeced8c7f115327ee61a961cfa80b72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc053ddb351745bde479c15eaa65ef3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gacc053ddb351745bde479c15eaa65ef3c">XCRE_COEF07_VPHASE0_OFFSET</a>&#160;&#160;&#160;0x01DC</td></tr>
<tr class="memdesc:gacc053ddb351745bde479c15eaa65ef3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 07 of vertical phase 0 filter.  <a href="group__cresample__v4__0.html#gacc053ddb351745bde479c15eaa65ef3c">More...</a><br /></td></tr>
<tr class="separator:gacc053ddb351745bde479c15eaa65ef3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86669b482b630a76ab12288e10cf14a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga86669b482b630a76ab12288e10cf14a1">XCRE_COEF00_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01E0</td></tr>
<tr class="memdesc:ga86669b482b630a76ab12288e10cf14a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 00 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga86669b482b630a76ab12288e10cf14a1">More...</a><br /></td></tr>
<tr class="separator:ga86669b482b630a76ab12288e10cf14a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga931197646d822c764861df2776be0167"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga931197646d822c764861df2776be0167">XCRE_COEF01_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01E4</td></tr>
<tr class="memdesc:ga931197646d822c764861df2776be0167"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 01 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga931197646d822c764861df2776be0167">More...</a><br /></td></tr>
<tr class="separator:ga931197646d822c764861df2776be0167"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95a3917c8d4a42c3d6b899644f339450"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga95a3917c8d4a42c3d6b899644f339450">XCRE_COEF02_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01E8</td></tr>
<tr class="memdesc:ga95a3917c8d4a42c3d6b899644f339450"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 02 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga95a3917c8d4a42c3d6b899644f339450">More...</a><br /></td></tr>
<tr class="separator:ga95a3917c8d4a42c3d6b899644f339450"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40dd8790c5c98b49c7e432800abcbe6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga40dd8790c5c98b49c7e432800abcbe6c">XCRE_COEF03_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01EC</td></tr>
<tr class="memdesc:ga40dd8790c5c98b49c7e432800abcbe6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 03 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga40dd8790c5c98b49c7e432800abcbe6c">More...</a><br /></td></tr>
<tr class="separator:ga40dd8790c5c98b49c7e432800abcbe6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0698f4c5311e2f9147c38905433bb66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf0698f4c5311e2f9147c38905433bb66">XCRE_COEF04_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01F0</td></tr>
<tr class="memdesc:gaf0698f4c5311e2f9147c38905433bb66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 04 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#gaf0698f4c5311e2f9147c38905433bb66">More...</a><br /></td></tr>
<tr class="separator:gaf0698f4c5311e2f9147c38905433bb66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10536f6834892f85f8f93059b4277a4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga10536f6834892f85f8f93059b4277a4a">XCRE_COEF05_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01F4</td></tr>
<tr class="memdesc:ga10536f6834892f85f8f93059b4277a4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 05 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga10536f6834892f85f8f93059b4277a4a">More...</a><br /></td></tr>
<tr class="separator:ga10536f6834892f85f8f93059b4277a4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20b5afe016e5879356b7e613c2fa4949"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga20b5afe016e5879356b7e613c2fa4949">XCRE_COEF06_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01F8</td></tr>
<tr class="memdesc:ga20b5afe016e5879356b7e613c2fa4949"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 06 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga20b5afe016e5879356b7e613c2fa4949">More...</a><br /></td></tr>
<tr class="separator:ga20b5afe016e5879356b7e613c2fa4949"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga101e8262084e88b2f8f7cff884fe06b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga101e8262084e88b2f8f7cff884fe06b7">XCRE_COEF07_VPHASE1_OFFSET</a>&#160;&#160;&#160;0x01FC</td></tr>
<tr class="memdesc:ga101e8262084e88b2f8f7cff884fe06b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient 07 of vertical phase 1 filter.  <a href="group__cresample__v4__0.html#ga101e8262084e88b2f8f7cff884fe06b7">More...</a><br /></td></tr>
<tr class="separator:ga101e8262084e88b2f8f7cff884fe06b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4bcf4304e9aaf163c07d8b27755f06c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a4bcf4304e9aaf163c07d8b27755f06c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input operations.  <a href="#a4bcf4304e9aaf163c07d8b27755f06c0">More...</a><br /></td></tr>
<tr class="separator:a4bcf4304e9aaf163c07d8b27755f06c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab6f8306121516322a43ce0143ef94601"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ab6f8306121516322a43ce0143ef94601"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output operations.  <a href="#ab6f8306121516322a43ce0143ef94601">More...</a><br /></td></tr>
<tr class="separator:ab6f8306121516322a43ce0143ef94601"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a383c98c6cf46b5c9e1c40124950e03e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a383c98c6cf46b5c9e1c40124950e03e4">XCresample_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:a383c98c6cf46b5c9e1c40124950e03e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="#a383c98c6cf46b5c9e1c40124950e03e4">More...</a><br /></td></tr>
<tr class="separator:a383c98c6cf46b5c9e1c40124950e03e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a644ad0f957bb97d33f18cab706e145d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a644ad0f957bb97d33f18cab706e145d5">XCresample_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a644ad0f957bb97d33f18cab706e145d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes into the given register.  <a href="#a644ad0f957bb97d33f18cab706e145d5">More...</a><br /></td></tr>
<tr class="separator:a644ad0f957bb97d33f18cab706e145d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">register offsets</div></td></tr>
<tr class="memitem:gae36d057ec512e3bf6ad23aedeca87287"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gae36d057ec512e3bf6ad23aedeca87287">XCRE_CONTROL_OFFSET</a>&#160;&#160;&#160;0x0000</td></tr>
<tr class="memdesc:gae36d057ec512e3bf6ad23aedeca87287"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control.  <a href="group__cresample__v4__0.html#gae36d057ec512e3bf6ad23aedeca87287">More...</a><br /></td></tr>
<tr class="separator:gae36d057ec512e3bf6ad23aedeca87287"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga87730ba30704098d260a67036eaa6f01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">XCRE_STATUS_OFFSET</a>&#160;&#160;&#160;0x0004</td></tr>
<tr class="memdesc:ga87730ba30704098d260a67036eaa6f01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status.  <a href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">More...</a><br /></td></tr>
<tr class="separator:ga87730ba30704098d260a67036eaa6f01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90090b9e9473a0bacec29831cd865434"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga90090b9e9473a0bacec29831cd865434">XCRE_ERROR_OFFSET</a>&#160;&#160;&#160;0x0008</td></tr>
<tr class="memdesc:ga90090b9e9473a0bacec29831cd865434"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error.  <a href="group__cresample__v4__0.html#ga90090b9e9473a0bacec29831cd865434">More...</a><br /></td></tr>
<tr class="separator:ga90090b9e9473a0bacec29831cd865434"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18c102d15e143b84399c8795212975e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a>&#160;&#160;&#160;0x000C</td></tr>
<tr class="memdesc:ga18c102d15e143b84399c8795212975e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ enable.  <a href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">More...</a><br /></td></tr>
<tr class="separator:ga18c102d15e143b84399c8795212975e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50dc699fde66f657be0e8a9713f78497"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga50dc699fde66f657be0e8a9713f78497">XCRE_VERSION_OFFSET</a>&#160;&#160;&#160;0x0010</td></tr>
<tr class="memdesc:ga50dc699fde66f657be0e8a9713f78497"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version.  <a href="group__cresample__v4__0.html#ga50dc699fde66f657be0e8a9713f78497">More...</a><br /></td></tr>
<tr class="separator:ga50dc699fde66f657be0e8a9713f78497"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga388982bb23871efe6833330f79b12a94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga388982bb23871efe6833330f79b12a94">XCRE_SYSDEBUG0_OFFSET</a>&#160;&#160;&#160;0x0014</td></tr>
<tr class="memdesc:ga388982bb23871efe6833330f79b12a94"><td class="mdescLeft">&#160;</td><td class="mdescRight">System debug 0.  <a href="group__cresample__v4__0.html#ga388982bb23871efe6833330f79b12a94">More...</a><br /></td></tr>
<tr class="separator:ga388982bb23871efe6833330f79b12a94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf943cd6552984fa4ed43ecadab6035c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#gaf943cd6552984fa4ed43ecadab6035c0">XCRE_SYSDEBUG1_OFFSET</a>&#160;&#160;&#160;0x0018</td></tr>
<tr class="memdesc:gaf943cd6552984fa4ed43ecadab6035c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">System debug 1.  <a href="group__cresample__v4__0.html#gaf943cd6552984fa4ed43ecadab6035c0">More...</a><br /></td></tr>
<tr class="separator:gaf943cd6552984fa4ed43ecadab6035c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga46bc8755667307701c57d998f9bccbde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__cresample__v4__0.html#ga46bc8755667307701c57d998f9bccbde">XCRE_SYSDEBUG2_OFFSET</a>&#160;&#160;&#160;0x001C</td></tr>
<tr class="memdesc:ga46bc8755667307701c57d998f9bccbde"><td class="mdescLeft">&#160;</td><td class="mdescRight">System debug 2.  <a href="group__cresample__v4__0.html#ga46bc8755667307701c57d998f9bccbde">More...</a><br /></td></tr>
<tr class="separator:ga46bc8755667307701c57d998f9bccbde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control register bit masks</div></td></tr>
<tr class="memitem:a9f8f91473ed9544ea408ab041203f53c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a9f8f91473ed9544ea408ab041203f53c">XCRE_CTL_SW_EN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a9f8f91473ed9544ea408ab041203f53c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mask.  <a href="#a9f8f91473ed9544ea408ab041203f53c">More...</a><br /></td></tr>
<tr class="separator:a9f8f91473ed9544ea408ab041203f53c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a236624032067fc6eab9b512945e4a1dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a236624032067fc6eab9b512945e4a1dc">XCRE_CTL_RUE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a236624032067fc6eab9b512945e4a1dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register update mask.  <a href="#a236624032067fc6eab9b512945e4a1dc">More...</a><br /></td></tr>
<tr class="separator:a236624032067fc6eab9b512945e4a1dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa6df80e3d96127c39d26f776a692d67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#aaa6df80e3d96127c39d26f776a692d67">XCRE_CTL_BPE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:aaa6df80e3d96127c39d26f776a692d67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bypass mask.  <a href="#aaa6df80e3d96127c39d26f776a692d67">More...</a><br /></td></tr>
<tr class="separator:aaa6df80e3d96127c39d26f776a692d67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa66681b6d3d1c8d2d7901464355d323a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#aa66681b6d3d1c8d2d7901464355d323a">XCRE_CTL_TPE_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:aa66681b6d3d1c8d2d7901464355d323a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Test pattern mask.  <a href="#aa66681b6d3d1c8d2d7901464355d323a">More...</a><br /></td></tr>
<tr class="separator:aa66681b6d3d1c8d2d7901464355d323a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3cc43348b3242c3d57ec00b1d8a49f4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a3cc43348b3242c3d57ec00b1d8a49f4b">XCRE_CTL_AUTORESET_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:a3cc43348b3242c3d57ec00b1d8a49f4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software reset - Auto-synchronize to SOF mask.  <a href="#a3cc43348b3242c3d57ec00b1d8a49f4b">More...</a><br /></td></tr>
<tr class="separator:a3cc43348b3242c3d57ec00b1d8a49f4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59a892889d7e272380b3187f143e2497"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a59a892889d7e272380b3187f143e2497">XCRE_CTL_RESET_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:a59a892889d7e272380b3187f143e2497"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software reset - instantaneous mask.  <a href="#a59a892889d7e272380b3187f143e2497">More...</a><br /></td></tr>
<tr class="separator:a59a892889d7e272380b3187f143e2497"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt register bit masks. It is applicable for</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Status and IRQ_ENABLE Registers </p>
</div></td></tr>
<tr class="memitem:add6a498a6bc1c13fc01e91f510d342de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#add6a498a6bc1c13fc01e91f510d342de">XCRE_IXR_PROCS_STARTED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:add6a498a6bc1c13fc01e91f510d342de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Proc started mask.  <a href="#add6a498a6bc1c13fc01e91f510d342de">More...</a><br /></td></tr>
<tr class="separator:add6a498a6bc1c13fc01e91f510d342de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8051673328a6111720b8566bb3cf1526"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a8051673328a6111720b8566bb3cf1526">XCRE_IXR_EOF_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a8051673328a6111720b8566bb3cf1526"><td class="mdescLeft">&#160;</td><td class="mdescRight">End-Of-Frame mask.  <a href="#a8051673328a6111720b8566bb3cf1526">More...</a><br /></td></tr>
<tr class="separator:a8051673328a6111720b8566bb3cf1526"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a804ab6687773a6c4a87f1a0716000f19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a804ab6687773a6c4a87f1a0716000f19">XCRE_IXR_SE_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:a804ab6687773a6c4a87f1a0716000f19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Error mask.  <a href="#a804ab6687773a6c4a87f1a0716000f19">More...</a><br /></td></tr>
<tr class="separator:a804ab6687773a6c4a87f1a0716000f19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a97004e97b72f36a24dc2d91e19358a99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a97004e97b72f36a24dc2d91e19358a99">XCRE_IXR_ALLINTR_MASK</a>&#160;&#160;&#160;0x00010003U</td></tr>
<tr class="memdesc:a97004e97b72f36a24dc2d91e19358a99"><td class="mdescLeft">&#160;</td><td class="mdescRight">OR of all mask.  <a href="#a97004e97b72f36a24dc2d91e19358a99">More...</a><br /></td></tr>
<tr class="separator:a97004e97b72f36a24dc2d91e19358a99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Error register bit masks</div></td></tr>
<tr class="memitem:a0aacdca8b7990a1d6a0e965b213bb9bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a0aacdca8b7990a1d6a0e965b213bb9bc">XCRE_ERR_EOL_EARLY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a0aacdca8b7990a1d6a0e965b213bb9bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: End of Line Early mask.  <a href="#a0aacdca8b7990a1d6a0e965b213bb9bc">More...</a><br /></td></tr>
<tr class="separator:a0aacdca8b7990a1d6a0e965b213bb9bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1c7c77ababa0deda872bcf9585c1c13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ae1c7c77ababa0deda872bcf9585c1c13">XCRE_ERR_EOL_LATE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ae1c7c77ababa0deda872bcf9585c1c13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: End of Line Late mask.  <a href="#ae1c7c77ababa0deda872bcf9585c1c13">More...</a><br /></td></tr>
<tr class="separator:ae1c7c77ababa0deda872bcf9585c1c13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0df29969c8c503b72aa74ad6dbff8f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#aa0df29969c8c503b72aa74ad6dbff8f5">XCRE_ERR_SOF_EARLY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:aa0df29969c8c503b72aa74ad6dbff8f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: Start of Frame Early mask.  <a href="#aa0df29969c8c503b72aa74ad6dbff8f5">More...</a><br /></td></tr>
<tr class="separator:aa0df29969c8c503b72aa74ad6dbff8f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4e7b99b55f7e72e3617c0fe3b9e3826"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#aa4e7b99b55f7e72e3617c0fe3b9e3826">XCRE_ERR_SOF_LATE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:aa4e7b99b55f7e72e3617c0fe3b9e3826"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: Start of Frame Late mask.  <a href="#aa4e7b99b55f7e72e3617c0fe3b9e3826">More...</a><br /></td></tr>
<tr class="separator:aa4e7b99b55f7e72e3617c0fe3b9e3826"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Version register bit masks and shifts</div></td></tr>
<tr class="memitem:aa63888a3741a78b6a5d226ea9be119a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#aa63888a3741a78b6a5d226ea9be119a1">XCRE_VER_REV_NUM_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:aa63888a3741a78b6a5d226ea9be119a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Revision Number mask.  <a href="#aa63888a3741a78b6a5d226ea9be119a1">More...</a><br /></td></tr>
<tr class="separator:aa63888a3741a78b6a5d226ea9be119a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:accd4dbc5d507c4b6f4073d012ccb3400"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#accd4dbc5d507c4b6f4073d012ccb3400">XCRE_VER_PID_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:accd4dbc5d507c4b6f4073d012ccb3400"><td class="mdescLeft">&#160;</td><td class="mdescRight">Patch ID mask.  <a href="#accd4dbc5d507c4b6f4073d012ccb3400">More...</a><br /></td></tr>
<tr class="separator:accd4dbc5d507c4b6f4073d012ccb3400"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e27a69cfbd5cf9261e123ec223e59c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a3e27a69cfbd5cf9261e123ec223e59c3">XCRE_VER_REV_MASK</a>&#160;&#160;&#160;0x0000F000</td></tr>
<tr class="memdesc:a3e27a69cfbd5cf9261e123ec223e59c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Revision mask.  <a href="#a3e27a69cfbd5cf9261e123ec223e59c3">More...</a><br /></td></tr>
<tr class="separator:a3e27a69cfbd5cf9261e123ec223e59c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a744ff1670814ab8411605bd5610a37d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a744ff1670814ab8411605bd5610a37d4">XCRE_VER_MINOR_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:a744ff1670814ab8411605bd5610a37d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Minor mask.  <a href="#a744ff1670814ab8411605bd5610a37d4">More...</a><br /></td></tr>
<tr class="separator:a744ff1670814ab8411605bd5610a37d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d8d09eb21e1e968c0450cb7dd5d516a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a5d8d09eb21e1e968c0450cb7dd5d516a">XCRE_VER_MAJOR_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:a5d8d09eb21e1e968c0450cb7dd5d516a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Major mask.  <a href="#a5d8d09eb21e1e968c0450cb7dd5d516a">More...</a><br /></td></tr>
<tr class="separator:a5d8d09eb21e1e968c0450cb7dd5d516a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75692d332ef8386dd59f5ad60f72b7c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a75692d332ef8386dd59f5ad60f72b7c7">XCRE_VER_INTERNAL_SHIFT</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a75692d332ef8386dd59f5ad60f72b7c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Patch ID shift.  <a href="#a75692d332ef8386dd59f5ad60f72b7c7">More...</a><br /></td></tr>
<tr class="separator:a75692d332ef8386dd59f5ad60f72b7c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ad9bb0d2ce4b4a58e639c645e7bfb28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a4ad9bb0d2ce4b4a58e639c645e7bfb28">XCRE_VER_REV_SHIFT</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:a4ad9bb0d2ce4b4a58e639c645e7bfb28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Revision shift.  <a href="#a4ad9bb0d2ce4b4a58e639c645e7bfb28">More...</a><br /></td></tr>
<tr class="separator:a4ad9bb0d2ce4b4a58e639c645e7bfb28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2de0988a224c4f2c0ff2c8fb99c1edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ae2de0988a224c4f2c0ff2c8fb99c1edd">XCRE_VER_MINOR_SHIFT</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ae2de0988a224c4f2c0ff2c8fb99c1edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Minor shift.  <a href="#ae2de0988a224c4f2c0ff2c8fb99c1edd">More...</a><br /></td></tr>
<tr class="separator:ae2de0988a224c4f2c0ff2c8fb99c1edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab39e2e1a51ac5b83405a1409f3ad334a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ab39e2e1a51ac5b83405a1409f3ad334a">XCRE_VER_MAJOR_SHIFT</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ab39e2e1a51ac5b83405a1409f3ad334a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Major shift.  <a href="#ab39e2e1a51ac5b83405a1409f3ad334a">More...</a><br /></td></tr>
<tr class="separator:ab39e2e1a51ac5b83405a1409f3ad334a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Active size register bit masks and shifts</div></td></tr>
<tr class="memitem:a9f98cbfc1c9126ed40145387dc779b28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a9f98cbfc1c9126ed40145387dc779b28">XCRE_ACTSIZE_NUM_PIXEL_MASK</a>&#160;&#160;&#160;0x00001FFF</td></tr>
<tr class="memdesc:a9f98cbfc1c9126ed40145387dc779b28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Active pixels per scan line (horizontal) mask.  <a href="#a9f98cbfc1c9126ed40145387dc779b28">More...</a><br /></td></tr>
<tr class="separator:a9f98cbfc1c9126ed40145387dc779b28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a705f25b13c7ec6c14dbbab653e263fe6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a705f25b13c7ec6c14dbbab653e263fe6">XCRE_ACTSIZE_NUM_LINE_MASK</a>&#160;&#160;&#160;0x1FFF0000</td></tr>
<tr class="memdesc:a705f25b13c7ec6c14dbbab653e263fe6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Active lines per frame (Vertical) mask.  <a href="#a705f25b13c7ec6c14dbbab653e263fe6">More...</a><br /></td></tr>
<tr class="separator:a705f25b13c7ec6c14dbbab653e263fe6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adea884db969de650a972cc4bd46ada60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#adea884db969de650a972cc4bd46ada60">XCRE_ACTSIZE_NUM_LINE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:adea884db969de650a972cc4bd46ada60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for number of lines.  <a href="#adea884db969de650a972cc4bd46ada60">More...</a><br /></td></tr>
<tr class="separator:adea884db969de650a972cc4bd46ada60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Encoding register bit masks and shifts</div></td></tr>
<tr class="memitem:a37fffbaea769fa911e7976283da2d7e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a37fffbaea769fa911e7976283da2d7e1">XCRE_ENCODING_FIELD_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:a37fffbaea769fa911e7976283da2d7e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Field parity mask.  <a href="#a37fffbaea769fa911e7976283da2d7e1">More...</a><br /></td></tr>
<tr class="separator:a37fffbaea769fa911e7976283da2d7e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf082abdad2a4087dd79c8e2fa86948b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#adf082abdad2a4087dd79c8e2fa86948b">XCRE_ENCODING_CHROMA_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:adf082abdad2a4087dd79c8e2fa86948b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Chroma parity mask.  <a href="#adf082abdad2a4087dd79c8e2fa86948b">More...</a><br /></td></tr>
<tr class="separator:adf082abdad2a4087dd79c8e2fa86948b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20167cee94dcbf66c85a5390d489ffa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a20167cee94dcbf66c85a5390d489ffa6">XCRE_ENCODING_FIELD_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:a20167cee94dcbf66c85a5390d489ffa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Field parity shift.  <a href="#a20167cee94dcbf66c85a5390d489ffa6">More...</a><br /></td></tr>
<tr class="separator:a20167cee94dcbf66c85a5390d489ffa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55f16d3c79938d89a5f0f0fa10621800"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a55f16d3c79938d89a5f0f0fa10621800">XCRE_ENCODING_CHROMA_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a55f16d3c79938d89a5f0f0fa10621800"><td class="mdescLeft">&#160;</td><td class="mdescRight">Chroma parity shift.  <a href="#a55f16d3c79938d89a5f0f0fa10621800">More...</a><br /></td></tr>
<tr class="separator:a55f16d3c79938d89a5f0f0fa10621800"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Coefficient bit mask and shift</div></td></tr>
<tr class="memitem:a8237f945f6c7bda0545995089bf6a5f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a8237f945f6c7bda0545995089bf6a5f6">XCRE_COEFF_FRAC_MASK</a>&#160;&#160;&#160;0x00003FFF</td></tr>
<tr class="memdesc:a8237f945f6c7bda0545995089bf6a5f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of Fractional part.  <a href="#a8237f945f6c7bda0545995089bf6a5f6">More...</a><br /></td></tr>
<tr class="separator:a8237f945f6c7bda0545995089bf6a5f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43ce2626e26ec592981c9fff31c4355e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a43ce2626e26ec592981c9fff31c4355e">XCRE_COEF_DECI_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:a43ce2626e26ec592981c9fff31c4355e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of Decimal part.  <a href="#a43ce2626e26ec592981c9fff31c4355e">More...</a><br /></td></tr>
<tr class="separator:a43ce2626e26ec592981c9fff31c4355e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afeba8102493e8d68f3711c0de474215e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#afeba8102493e8d68f3711c0de474215e">XCRE_COEF_SIGN_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:afeba8102493e8d68f3711c0de474215e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Coefficient sign bit.  <a href="#afeba8102493e8d68f3711c0de474215e">More...</a><br /></td></tr>
<tr class="separator:afeba8102493e8d68f3711c0de474215e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a0413d42fb2ca474c0887652e0b28d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a6a0413d42fb2ca474c0887652e0b28d2">XCRE_COEFF_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:a6a0413d42fb2ca474c0887652e0b28d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient mask.  <a href="#a6a0413d42fb2ca474c0887652e0b28d2">More...</a><br /></td></tr>
<tr class="separator:a6a0413d42fb2ca474c0887652e0b28d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a000906b27b64ea3a083b8dcf82d8cda6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a000906b27b64ea3a083b8dcf82d8cda6">XCRE_COEFF_SHIFT</a>&#160;&#160;&#160;14</td></tr>
<tr class="memdesc:a000906b27b64ea3a083b8dcf82d8cda6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for decimal value.  <a href="#a000906b27b64ea3a083b8dcf82d8cda6">More...</a><br /></td></tr>
<tr class="separator:a000906b27b64ea3a083b8dcf82d8cda6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b6c6d8486f87ee7e560f524905c18e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a3b6c6d8486f87ee7e560f524905c18e6">XCRE_COEFF_SIGN_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a3b6c6d8486f87ee7e560f524905c18e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coefficient shift.  <a href="#a3b6c6d8486f87ee7e560f524905c18e6">More...</a><br /></td></tr>
<tr class="separator:a3b6c6d8486f87ee7e560f524905c18e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">General purpose macros</div></td></tr>
<tr class="memitem:a00023e17dea7a5309d4f9119236654a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a00023e17dea7a5309d4f9119236654a5">XCRE_SIGN_MUL</a>&#160;&#160;&#160;-1</td></tr>
<tr class="memdesc:a00023e17dea7a5309d4f9119236654a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro for sign multiplication.  <a href="#a00023e17dea7a5309d4f9119236654a5">More...</a><br /></td></tr>
<tr class="separator:a00023e17dea7a5309d4f9119236654a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a400cf6478aacc983fc48d21e0a5880ab"><td class="memItemLeft" align="right" valign="top"><a id="a400cf6478aacc983fc48d21e0a5880ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XCRE_SIGNBIT_MASK</b></td></tr>
<tr class="separator:a400cf6478aacc983fc48d21e0a5880ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a344ef55f48597146bf99310cca308756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a344ef55f48597146bf99310cca308756">XCRE_MAX_VALUE</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:a344ef55f48597146bf99310cca308756"><td class="mdescLeft">&#160;</td><td class="mdescRight">32 bit maximum value  <a href="#a344ef55f48597146bf99310cca308756">More...</a><br /></td></tr>
<tr class="separator:a344ef55f48597146bf99310cca308756"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">backward compatibility macros</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>To support backward compatibility following macro definition are re-defined. </p>
</div></td></tr>
<tr class="memitem:ab08ae72b28eb517952669e8059a57438"><td class="memItemLeft" align="right" valign="top"><a id="ab08ae72b28eb517952669e8059a57438"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_CONTROL</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gae36d057ec512e3bf6ad23aedeca87287">XCRE_CONTROL_OFFSET</a></td></tr>
<tr class="separator:ab08ae72b28eb517952669e8059a57438"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa6f6b04b3cc0360a21ec4839cd4f03ec"><td class="memItemLeft" align="right" valign="top"><a id="aa6f6b04b3cc0360a21ec4839cd4f03ec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_STATUS</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">XCRE_STATUS_OFFSET</a></td></tr>
<tr class="separator:aa6f6b04b3cc0360a21ec4839cd4f03ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a554f66180e7658e5ddb6471f6636ae39"><td class="memItemLeft" align="right" valign="top"><a id="a554f66180e7658e5ddb6471f6636ae39"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_ERROR</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga90090b9e9473a0bacec29831cd865434">XCRE_ERROR_OFFSET</a></td></tr>
<tr class="separator:a554f66180e7658e5ddb6471f6636ae39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95a95ab44d457cbddc71696a216a05fd"><td class="memItemLeft" align="right" valign="top"><a id="a95a95ab44d457cbddc71696a216a05fd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_IRQ_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a></td></tr>
<tr class="separator:a95a95ab44d457cbddc71696a216a05fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a517507a6f422841239aa4b79c3106c78"><td class="memItemLeft" align="right" valign="top"><a id="a517507a6f422841239aa4b79c3106c78"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_VERSION</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga50dc699fde66f657be0e8a9713f78497">XCRE_VERSION_OFFSET</a></td></tr>
<tr class="separator:a517507a6f422841239aa4b79c3106c78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab82be2cd90cf13a336d10dd569c87837"><td class="memItemLeft" align="right" valign="top"><a id="ab82be2cd90cf13a336d10dd569c87837"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_SYSDEBUG0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga388982bb23871efe6833330f79b12a94">XCRE_SYSDEBUG0_OFFSET</a></td></tr>
<tr class="separator:ab82be2cd90cf13a336d10dd569c87837"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee458faa4102e875ef0900c8f7f690e5"><td class="memItemLeft" align="right" valign="top"><a id="aee458faa4102e875ef0900c8f7f690e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_SYSDEBUG1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaf943cd6552984fa4ed43ecadab6035c0">XCRE_SYSDEBUG1_OFFSET</a></td></tr>
<tr class="separator:aee458faa4102e875ef0900c8f7f690e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72b81214f487f323fcdf3598f2bfe8b9"><td class="memItemLeft" align="right" valign="top"><a id="a72b81214f487f323fcdf3598f2bfe8b9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_SYSDEBUG2</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga46bc8755667307701c57d998f9bccbde">XCRE_SYSDEBUG2_OFFSET</a></td></tr>
<tr class="separator:a72b81214f487f323fcdf3598f2bfe8b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac703035cac182fd2215830d408eacc54"><td class="memItemLeft" align="right" valign="top"><a id="ac703035cac182fd2215830d408eacc54"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_ACTIVE_SIZE</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga2fabb0e08576485f3f54cd1f4531024a">XCRE_ACTIVE_SIZE_OFFSET</a></td></tr>
<tr class="separator:ac703035cac182fd2215830d408eacc54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53d4ce09d2cec8a76533235dd257bfdc"><td class="memItemLeft" align="right" valign="top"><a id="a53d4ce09d2cec8a76533235dd257bfdc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_ENCODING</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga0b1a96d8791a35a4cbb98d7be3f27b5a">XCRE_ENCODING_OFFSET</a></td></tr>
<tr class="separator:a53d4ce09d2cec8a76533235dd257bfdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58a2d5bafad7d89982686b5c754e8166"><td class="memItemLeft" align="right" valign="top"><a id="a58a2d5bafad7d89982686b5c754e8166"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF00_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gab08648fa4329ccb2f1f792c049d0d96e">XCRE_COEF00_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a58a2d5bafad7d89982686b5c754e8166"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade7fe09fa42649144d200bba3b2a1bd0"><td class="memItemLeft" align="right" valign="top"><a id="ade7fe09fa42649144d200bba3b2a1bd0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF01_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaf45ea16c39ab86263617c9f72733a5ec">XCRE_COEF01_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:ade7fe09fa42649144d200bba3b2a1bd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9bad685ccdf0a3bf926758dc30050aa"><td class="memItemLeft" align="right" valign="top"><a id="ab9bad685ccdf0a3bf926758dc30050aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF02_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gae1c4e8aa886cb44126fb45f54d4d2561">XCRE_COEF02_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:ab9bad685ccdf0a3bf926758dc30050aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d06c46b21e20ba09e5b5dbeecaae9bd"><td class="memItemLeft" align="right" valign="top"><a id="a6d06c46b21e20ba09e5b5dbeecaae9bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF03_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaa661ff07f1c20ab1839c9a85fca60571">XCRE_COEF03_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a6d06c46b21e20ba09e5b5dbeecaae9bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace98dcc7d246d6eac5c01d5d08fe9669"><td class="memItemLeft" align="right" valign="top"><a id="ace98dcc7d246d6eac5c01d5d08fe9669"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF04_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gafdc160496035e2d1c64e1f6855356681">XCRE_COEF04_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:ace98dcc7d246d6eac5c01d5d08fe9669"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a356cc228c722da4c2e5fdc435b6aa797"><td class="memItemLeft" align="right" valign="top"><a id="a356cc228c722da4c2e5fdc435b6aa797"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF05_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga02e0f97aa30b4805922757f17e0b12cd">XCRE_COEF05_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a356cc228c722da4c2e5fdc435b6aa797"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a69be42b208bc0a8beefbc5dfafd76089"><td class="memItemLeft" align="right" valign="top"><a id="a69be42b208bc0a8beefbc5dfafd76089"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF06_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga9a56ac84b8403ceece66d68623c3a091">XCRE_COEF06_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a69be42b208bc0a8beefbc5dfafd76089"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adcf18fd321b5f52dd69dbc8b30483d21"><td class="memItemLeft" align="right" valign="top"><a id="adcf18fd321b5f52dd69dbc8b30483d21"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF07_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga95a23cf13a13e9186541d1aaaae78966">XCRE_COEF07_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:adcf18fd321b5f52dd69dbc8b30483d21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1a48f1f198af479afbb734aa2c8c1a3"><td class="memItemLeft" align="right" valign="top"><a id="ad1a48f1f198af479afbb734aa2c8c1a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF08_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga06bd5b0189a2bfc254383e64e1b1ba70">XCRE_COEF08_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:ad1a48f1f198af479afbb734aa2c8c1a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d20cda72b7833d92fba2379d33b5400"><td class="memItemLeft" align="right" valign="top"><a id="a7d20cda72b7833d92fba2379d33b5400"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF09_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga45c917cbe5b9acdc47758738a71d08f9">XCRE_COEF09_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a7d20cda72b7833d92fba2379d33b5400"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a86ee8b8be3deb3a57b47374a5baf23ac"><td class="memItemLeft" align="right" valign="top"><a id="a86ee8b8be3deb3a57b47374a5baf23ac"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF10_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga327a4b079f7630c0efc499590035d2f5">XCRE_COEF10_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a86ee8b8be3deb3a57b47374a5baf23ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a93b38d0a36ffb61e6974c49e491d15bc"><td class="memItemLeft" align="right" valign="top"><a id="a93b38d0a36ffb61e6974c49e491d15bc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF11_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga7ccae86cacb8f7938a000ef7b2b340b3">XCRE_COEF11_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:a93b38d0a36ffb61e6974c49e491d15bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad50675fb39c551dfe7dded9d956470a9"><td class="memItemLeft" align="right" valign="top"><a id="ad50675fb39c551dfe7dded9d956470a9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF12_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaadd607ad747e8eced4dfa42c24f1b210">XCRE_COEF12_HPHASE0_OFFSET</a></td></tr>
<tr class="separator:ad50675fb39c551dfe7dded9d956470a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8de235a55513c790aecd0989d5ea9bfd"><td class="memItemLeft" align="right" valign="top"><a id="a8de235a55513c790aecd0989d5ea9bfd"></a>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF19_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga106e8fddab9ff751602884fbd58f9332">XCRE_COEF19_HPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF20_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga98e024bc3a1c98c73e7858fcba25d8bb">XCRE_COEF20_HPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF21_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga0f9df4d920cc235338a1acd1f452ba8b">XCRE_COEF21_HPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF22_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaf80e94e18e368f0120b46986f9dfdad9">XCRE_COEF22_HPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF23_HPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga43f073717f0cd43bf75b3f51f927307f">XCRE_COEF23_HPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF00_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga1ad7438e92fb57b98c26f50645a9575f">XCRE_COEF00_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF01_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga8f48d6fb21b46e73c7af5a0b9c01e155">XCRE_COEF01_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF02_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gafaf168f142154b67616c59cf9827becb">XCRE_COEF02_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF03_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga34b5d6d0f4bb4d418788b19e5bda0a72">XCRE_COEF03_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF04_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga9d7be6ce93a5d3f38132fff3a3993398">XCRE_COEF04_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF05_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaac9a0d2f1f791b58c0318170c9ff19c1">XCRE_COEF05_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF06_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gabde07b24b8a06faaa6afea4babf96cb4">XCRE_COEF06_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF11_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaad22ec3304706b2f7bd65477092dcc48">XCRE_COEF11_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF13_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga7658dbc810aa4b13f63121f26dc44ab2">XCRE_COEF13_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF14_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gae79641e31df71116fc605d5386a18df2">XCRE_COEF14_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF15_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga0c62d9914671287c36bf1da711dc391d">XCRE_COEF15_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF16_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga3b47a1512cdb344615d915c6a453e882">XCRE_COEF16_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF20_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gacf7cb29773e11a645b50a551279a5bf5">XCRE_COEF20_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF22_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga7270ab4cf94edeed371f32494e8c99d7">XCRE_COEF22_HPHASE1_OFFSET</a></td></tr>
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<tr class="memitem:a5781c73b1e03b0d71ba3a0cf1060815d"><td class="memItemLeft" align="right" valign="top"><a id="a5781c73b1e03b0d71ba3a0cf1060815d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF23_HPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaae4cbb76dfe9b462d729aea1f24b172c">XCRE_COEF23_HPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF00_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga7c618712800d861c59fb9deefd45a2b6">XCRE_COEF00_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF01_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaac06a91cdd2b2a82b72724082d82b42b">XCRE_COEF01_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF02_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gae68fe139eec3456e8436d45d375f93fb">XCRE_COEF02_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF03_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga61fe2e129ee73467a333bde971a09ab1">XCRE_COEF03_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF04_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga960e2dce62f01924ee5a8082ba5a77f2">XCRE_COEF04_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF05_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga7adb9cc708f775c981b14d40fe66f017">XCRE_COEF05_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF06_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gabbeced8c7f115327ee61a961cfa80b72">XCRE_COEF06_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF07_VPHASE0</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gacc053ddb351745bde479c15eaa65ef3c">XCRE_COEF07_VPHASE0_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF00_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga86669b482b630a76ab12288e10cf14a1">XCRE_COEF00_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF01_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga931197646d822c764861df2776be0167">XCRE_COEF01_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF02_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga95a3917c8d4a42c3d6b899644f339450">XCRE_COEF02_VPHASE1_OFFSET</a></td></tr>
<tr class="separator:a18644f4eb44a4a5fe36af75c7a223d23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0aec6a4f87741f24d6e90817d4fc42f1"><td class="memItemLeft" align="right" valign="top"><a id="a0aec6a4f87741f24d6e90817d4fc42f1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF03_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga40dd8790c5c98b49c7e432800abcbe6c">XCRE_COEF03_VPHASE1_OFFSET</a></td></tr>
<tr class="separator:a0aec6a4f87741f24d6e90817d4fc42f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF04_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#gaf0698f4c5311e2f9147c38905433bb66">XCRE_COEF04_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF05_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga10536f6834892f85f8f93059b4277a4a">XCRE_COEF05_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF06_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga20b5afe016e5879356b7e613c2fa4949">XCRE_COEF06_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_COEF07_VPHASE1</b>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga101e8262084e88b2f8f7cff884fe06b7">XCRE_COEF07_VPHASE1_OFFSET</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_CTL_EN_MASK</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a9f8f91473ed9544ea408ab041203f53c">XCRE_CTL_SW_EN_MASK</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_CTL_RU_MASK</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a236624032067fc6eab9b512945e4a1dc">XCRE_CTL_RUE_MASK</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_CTL_AUTORESET</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a3cc43348b3242c3d57ec00b1d8a49f4b">XCRE_CTL_AUTORESET_MASK</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_CTL_RESET</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a59a892889d7e272380b3187f143e2497">XCRE_CTL_RESET_MASK</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_In32</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_Out32</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_ReadReg</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a383c98c6cf46b5c9e1c40124950e03e4">XCresample_ReadReg</a></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CRESAMPLE_WriteReg</b>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a644ad0f957bb97d33f18cab706e145d5">XCresample_WriteReg</a></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt registers</div></td></tr>
<tr class="memitem:a9a38a8abeb63a5dcfbce4e1f57cf7c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#a9a38a8abeb63a5dcfbce4e1f57cf7c97">XCRE_ISR_OFFSET</a>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">XCRE_STATUS_OFFSET</a></td></tr>
<tr class="memdesc:a9a38a8abeb63a5dcfbce4e1f57cf7c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt status register.  <a href="#a9a38a8abeb63a5dcfbce4e1f57cf7c97">More...</a><br /></td></tr>
<tr class="separator:a9a38a8abeb63a5dcfbce4e1f57cf7c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6f21d36c462bfb1d0bd91cfa72762aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xcresample__hw_8h.html#ae6f21d36c462bfb1d0bd91cfa72762aa">XCRE_IER_OFFSET</a>&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a></td></tr>
<tr class="memdesc:ae6f21d36c462bfb1d0bd91cfa72762aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable <a href="#ae6f21d36c462bfb1d0bd91cfa72762aa">More...</a><br /></td></tr>
<tr class="separator:ae6f21d36c462bfb1d0bd91cfa72762aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="a705f25b13c7ec6c14dbbab653e263fe6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a705f25b13c7ec6c14dbbab653e263fe6">&#9670;&nbsp;</a></span>XCRE_ACTSIZE_NUM_LINE_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_ACTSIZE_NUM_LINE_MASK&#160;&#160;&#160;0x1FFF0000</td>
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</div><div class="memdoc">

<p>Number of Active lines per frame (Vertical) mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>.</p>

</div>
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<a id="adea884db969de650a972cc4bd46ada60"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adea884db969de650a972cc4bd46ada60">&#9670;&nbsp;</a></span>XCRE_ACTSIZE_NUM_LINE_SHIFT</h2>

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          <td class="memname">#define XCRE_ACTSIZE_NUM_LINE_SHIFT&#160;&#160;&#160;16</td>
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      </table>
</div><div class="memdoc">

<p>Shift for number of lines. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>, and <a class="el" href="group__cresample__v4__0.html#gaa92fd02ee15f7f102dde33a7b2d904d3">XCresample_SetActiveSize()</a>.</p>

</div>
</div>
<a id="a9f98cbfc1c9126ed40145387dc779b28"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9f98cbfc1c9126ed40145387dc779b28">&#9670;&nbsp;</a></span>XCRE_ACTSIZE_NUM_PIXEL_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_ACTSIZE_NUM_PIXEL_MASK&#160;&#160;&#160;0x00001FFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of Active pixels per scan line (horizontal) mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>.</p>

</div>
</div>
<a id="a43ce2626e26ec592981c9fff31c4355e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a43ce2626e26ec592981c9fff31c4355e">&#9670;&nbsp;</a></span>XCRE_COEF_DECI_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_COEF_DECI_MASK&#160;&#160;&#160;0x00004000</td>
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<p>Mask of Decimal part. </p>

</div>
</div>
<a id="afeba8102493e8d68f3711c0de474215e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afeba8102493e8d68f3711c0de474215e">&#9670;&nbsp;</a></span>XCRE_COEF_SIGN_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_COEF_SIGN_MASK&#160;&#160;&#160;0x00008000</td>
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</div><div class="memdoc">

<p>Mask for Coefficient sign bit. </p>

</div>
</div>
<a id="a8237f945f6c7bda0545995089bf6a5f6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8237f945f6c7bda0545995089bf6a5f6">&#9670;&nbsp;</a></span>XCRE_COEFF_FRAC_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_COEFF_FRAC_MASK&#160;&#160;&#160;0x00003FFF</td>
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<p>Mask of Fractional part. </p>

</div>
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<a id="a6a0413d42fb2ca474c0887652e0b28d2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6a0413d42fb2ca474c0887652e0b28d2">&#9670;&nbsp;</a></span>XCRE_COEFF_MASK</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_COEFF_MASK&#160;&#160;&#160;0x0000FFFF</td>
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<p>Coefficient mask. </p>

</div>
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<a id="a000906b27b64ea3a083b8dcf82d8cda6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a000906b27b64ea3a083b8dcf82d8cda6">&#9670;&nbsp;</a></span>XCRE_COEFF_SHIFT</h2>

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          <td class="memname">#define XCRE_COEFF_SHIFT&#160;&#160;&#160;14</td>
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<p>Shift for decimal value. </p>

</div>
</div>
<a id="a3b6c6d8486f87ee7e560f524905c18e6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3b6c6d8486f87ee7e560f524905c18e6">&#9670;&nbsp;</a></span>XCRE_COEFF_SIGN_SHIFT</h2>

<div class="memitem">
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          <td class="memname">#define XCRE_COEFF_SIGN_SHIFT&#160;&#160;&#160;16</td>
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<p>Coefficient shift. </p>

</div>
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<a id="a3cc43348b3242c3d57ec00b1d8a49f4b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3cc43348b3242c3d57ec00b1d8a49f4b">&#9670;&nbsp;</a></span>XCRE_CTL_AUTORESET_MASK</h2>

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      <table class="memname">
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          <td class="memname">#define XCRE_CTL_AUTORESET_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Software reset - Auto-synchronize to SOF mask. </p>

</div>
</div>
<a id="aaa6df80e3d96127c39d26f776a692d67"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaa6df80e3d96127c39d26f776a692d67">&#9670;&nbsp;</a></span>XCRE_CTL_BPE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_CTL_BPE_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bypass mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, and <a class="el" href="group__cresample__v4__0.html#gae8267377a15da7e199a393c47baf42e1">XCresample_IsDbgByPassEnabled()</a>.</p>

</div>
</div>
<a id="a59a892889d7e272380b3187f143e2497"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a59a892889d7e272380b3187f143e2497">&#9670;&nbsp;</a></span>XCRE_CTL_RESET_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_CTL_RESET_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Software reset - instantaneous mask. </p>

</div>
</div>
<a id="a236624032067fc6eab9b512945e4a1dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a236624032067fc6eab9b512945e4a1dc">&#9670;&nbsp;</a></span>XCRE_CTL_RUE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_CTL_RUE_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register update mask. </p>

</div>
</div>
<a id="a9f8f91473ed9544ea408ab041203f53c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9f8f91473ed9544ea408ab041203f53c">&#9670;&nbsp;</a></span>XCRE_CTL_SW_EN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_CTL_SW_EN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable mask. </p>

</div>
</div>
<a id="aa66681b6d3d1c8d2d7901464355d323a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa66681b6d3d1c8d2d7901464355d323a">&#9670;&nbsp;</a></span>XCRE_CTL_TPE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_CTL_TPE_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Test pattern mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, and <a class="el" href="group__cresample__v4__0.html#gae8fb855ff8ece1b628d69f9cd0eebd5a">XCresample_IsDbgTestPatternEnabled()</a>.</p>

</div>
</div>
<a id="adf082abdad2a4087dd79c8e2fa86948b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adf082abdad2a4087dd79c8e2fa86948b">&#9670;&nbsp;</a></span>XCRE_ENCODING_CHROMA_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ENCODING_CHROMA_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Chroma parity mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>, and <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>.</p>

</div>
</div>
<a id="a55f16d3c79938d89a5f0f0fa10621800"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a55f16d3c79938d89a5f0f0fa10621800">&#9670;&nbsp;</a></span>XCRE_ENCODING_CHROMA_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ENCODING_CHROMA_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Chroma parity shift. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>.</p>

</div>
</div>
<a id="a37fffbaea769fa911e7976283da2d7e1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a37fffbaea769fa911e7976283da2d7e1">&#9670;&nbsp;</a></span>XCRE_ENCODING_FIELD_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ENCODING_FIELD_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Field parity mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>, and <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>.</p>

</div>
</div>
<a id="a20167cee94dcbf66c85a5390d489ffa6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a20167cee94dcbf66c85a5390d489ffa6">&#9670;&nbsp;</a></span>XCRE_ENCODING_FIELD_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ENCODING_FIELD_SHIFT&#160;&#160;&#160;7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Field parity shift. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>.</p>

</div>
</div>
<a id="a0aacdca8b7990a1d6a0e965b213bb9bc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0aacdca8b7990a1d6a0e965b213bb9bc">&#9670;&nbsp;</a></span>XCRE_ERR_EOL_EARLY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ERR_EOL_EARLY_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error: End of Line Early mask. </p>

</div>
</div>
<a id="ae1c7c77ababa0deda872bcf9585c1c13"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae1c7c77ababa0deda872bcf9585c1c13">&#9670;&nbsp;</a></span>XCRE_ERR_EOL_LATE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ERR_EOL_LATE_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error: End of Line Late mask. </p>

</div>
</div>
<a id="aa0df29969c8c503b72aa74ad6dbff8f5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa0df29969c8c503b72aa74ad6dbff8f5">&#9670;&nbsp;</a></span>XCRE_ERR_SOF_EARLY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ERR_SOF_EARLY_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error: Start of Frame Early mask. </p>

</div>
</div>
<a id="aa4e7b99b55f7e72e3617c0fe3b9e3826"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa4e7b99b55f7e72e3617c0fe3b9e3826">&#9670;&nbsp;</a></span>XCRE_ERR_SOF_LATE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ERR_SOF_LATE_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error: Start of Frame Late mask. </p>

</div>
</div>
<a id="ae6f21d36c462bfb1d0bd91cfa72762aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae6f21d36c462bfb1d0bd91cfa72762aa">&#9670;&nbsp;</a></span>XCRE_IER_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_IER_OFFSET&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga18c102d15e143b84399c8795212975e8">XCRE_IRQ_EN_OFFSET</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt enable</p>
<p>*..register corresponds to status bits </p>

</div>
</div>
<a id="a9a38a8abeb63a5dcfbce4e1f57cf7c97"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9a38a8abeb63a5dcfbce4e1f57cf7c97">&#9670;&nbsp;</a></span>XCRE_ISR_OFFSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_ISR_OFFSET&#160;&#160;&#160;<a class="el" href="group__cresample__v4__0.html#ga87730ba30704098d260a67036eaa6f01">XCRE_STATUS_OFFSET</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt status register. </p>

</div>
</div>
<a id="a97004e97b72f36a24dc2d91e19358a99"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a97004e97b72f36a24dc2d91e19358a99">&#9670;&nbsp;</a></span>XCRE_IXR_ALLINTR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_IXR_ALLINTR_MASK&#160;&#160;&#160;0x00010003U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>OR of all mask. </p>

</div>
</div>
<a id="a8051673328a6111720b8566bb3cf1526"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8051673328a6111720b8566bb3cf1526">&#9670;&nbsp;</a></span>XCRE_IXR_EOF_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_IXR_EOF_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>End-Of-Frame mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

</div>
</div>
<a id="add6a498a6bc1c13fc01e91f510d342de"></a>
<h2 class="memtitle"><span class="permalink"><a href="#add6a498a6bc1c13fc01e91f510d342de">&#9670;&nbsp;</a></span>XCRE_IXR_PROCS_STARTED_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_IXR_PROCS_STARTED_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Proc started mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

</div>
</div>
<a id="a804ab6687773a6c4a87f1a0716000f19"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a804ab6687773a6c4a87f1a0716000f19">&#9670;&nbsp;</a></span>XCRE_IXR_SE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_IXR_SE_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Error mask. </p>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gad3db1c393abaf5003a47b95c7399d1b7">XCresample_IntrHandler()</a>.</p>

</div>
</div>
<a id="a344ef55f48597146bf99310cca308756"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a344ef55f48597146bf99310cca308756">&#9670;&nbsp;</a></span>XCRE_MAX_VALUE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_MAX_VALUE&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>32 bit maximum value </p>

</div>
</div>
<a id="a00023e17dea7a5309d4f9119236654a5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a00023e17dea7a5309d4f9119236654a5">&#9670;&nbsp;</a></span>XCRE_SIGN_MUL</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_SIGN_MUL&#160;&#160;&#160;-1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro for sign multiplication. </p>

</div>
</div>
<a id="a75692d332ef8386dd59f5ad60f72b7c7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a75692d332ef8386dd59f5ad60f72b7c7">&#9670;&nbsp;</a></span>XCRE_VER_INTERNAL_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_INTERNAL_SHIFT&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Patch ID shift. </p>

</div>
</div>
<a id="a5d8d09eb21e1e968c0450cb7dd5d516a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5d8d09eb21e1e968c0450cb7dd5d516a">&#9670;&nbsp;</a></span>XCRE_VER_MAJOR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_MAJOR_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Major mask. </p>

</div>
</div>
<a id="ab39e2e1a51ac5b83405a1409f3ad334a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab39e2e1a51ac5b83405a1409f3ad334a">&#9670;&nbsp;</a></span>XCRE_VER_MAJOR_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_MAJOR_SHIFT&#160;&#160;&#160;0x00000018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Major shift. </p>

</div>
</div>
<a id="a744ff1670814ab8411605bd5610a37d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a744ff1670814ab8411605bd5610a37d4">&#9670;&nbsp;</a></span>XCRE_VER_MINOR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_MINOR_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Minor mask. </p>

</div>
</div>
<a id="ae2de0988a224c4f2c0ff2c8fb99c1edd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae2de0988a224c4f2c0ff2c8fb99c1edd">&#9670;&nbsp;</a></span>XCRE_VER_MINOR_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_MINOR_SHIFT&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Minor shift. </p>

</div>
</div>
<a id="accd4dbc5d507c4b6f4073d012ccb3400"></a>
<h2 class="memtitle"><span class="permalink"><a href="#accd4dbc5d507c4b6f4073d012ccb3400">&#9670;&nbsp;</a></span>XCRE_VER_PID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_PID_MASK&#160;&#160;&#160;0x00000F00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Patch ID mask. </p>

</div>
</div>
<a id="a3e27a69cfbd5cf9261e123ec223e59c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3e27a69cfbd5cf9261e123ec223e59c3">&#9670;&nbsp;</a></span>XCRE_VER_REV_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_REV_MASK&#160;&#160;&#160;0x0000F000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Revision mask. </p>

</div>
</div>
<a id="aa63888a3741a78b6a5d226ea9be119a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa63888a3741a78b6a5d226ea9be119a1">&#9670;&nbsp;</a></span>XCRE_VER_REV_NUM_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_REV_NUM_MASK&#160;&#160;&#160;0x000000FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Revision Number mask. </p>

</div>
</div>
<a id="a4ad9bb0d2ce4b4a58e639c645e7bfb28"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4ad9bb0d2ce4b4a58e639c645e7bfb28">&#9670;&nbsp;</a></span>XCRE_VER_REV_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCRE_VER_REV_SHIFT&#160;&#160;&#160;0x0000000C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Revision shift. </p>

</div>
</div>
<a id="a4bcf4304e9aaf163c07d8b27755f06c0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4bcf4304e9aaf163c07d8b27755f06c0">&#9670;&nbsp;</a></span>XCresample_In32</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCresample_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input operations. </p>

</div>
</div>
<a id="ab6f8306121516322a43ce0143ef94601"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab6f8306121516322a43ce0143ef94601">&#9670;&nbsp;</a></span>XCresample_Out32</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCresample_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output operations. </p>

</div>
</div>
<a id="a383c98c6cf46b5c9e1c40124950e03e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a383c98c6cf46b5c9e1c40124950e03e4">&#9670;&nbsp;</a></span>XCresample_ReadReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCresample_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#a4bcf4304e9aaf163c07d8b27755f06c0">XCresample_In32</a>((BaseAddress) + (u32)(RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the Chroma Resampler core </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at top of this file)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xcresample__hw_8h.html#a383c98c6cf46b5c9e1c40124950e03e4" title="This macro reads the given register. ">XCresample_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#gad8b448647610e20e45f560ed50465d15">XCresample_GetActiveSize()</a>, <a class="el" href="group__cresample__v4__0.html#ga2871e4a4446a101e00ace372810342ce">XCresample_GetChromaParity()</a>, <a class="el" href="group__cresample__v4__0.html#gab4f2fab7cafe12c0dd55b63f8a4f9bb2">XCresample_GetDbgFrameCount()</a>, <a class="el" href="group__cresample__v4__0.html#ga81ee6e5159f9173134f5203f079c19d6">XCresample_GetDbgLineCount()</a>, <a class="el" href="group__cresample__v4__0.html#gadae07783fcaf65425e70d97648cbf04e">XCresample_GetDbgPixelCount()</a>, <a class="el" href="group__cresample__v4__0.html#ga3033cdcbecf61fea37bc9b1795636bf7">XCresample_GetFieldParity()</a>, <a class="el" href="group__cresample__v4__0.html#ga676b8cfd788ad69cd9c622e2a4953bed">XCresample_GetHCoefs()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd4ca76afc9607d8cc69afeb957b5f">XCresample_GetVCoefs()</a>, <a class="el" href="group__cresample__v4__0.html#ga759917fbb8599a22fdfe5619ce13a3b2">XCresample_GetVersion()</a>, <a class="el" href="group__cresample__v4__0.html#gae8267377a15da7e199a393c47baf42e1">XCresample_IsDbgByPassEnabled()</a>, <a class="el" href="group__cresample__v4__0.html#gae8fb855ff8ece1b628d69f9cd0eebd5a">XCresample_IsDbgTestPatternEnabled()</a>, <a class="el" href="group__cresample__v4__0.html#ga120e094a3de7a49d4b5e3808ad7fadd2">XCresample_SelfTest()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>, and <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>.</p>

</div>
</div>
<a id="a644ad0f957bb97d33f18cab706e145d5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a644ad0f957bb97d33f18cab706e145d5">&#9670;&nbsp;</a></span>XCresample_WriteReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XCresample_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xcresample__hw_8h.html#ab6f8306121516322a43ce0143ef94601">XCresample_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes into the given register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the Xilinx base address of the Chroma Resampler core </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at top of this file) </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XCresample_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__cresample__v4__0.html#ga1d749808d07e3987e21fb3ec7b54c3a2">XCresample_Clear_HCoef_Values()</a>, <a class="el" href="group__cresample__v4__0.html#gad3c15e9a7607730c4d6bab0bff8af610">XCresample_Clear_VCoef_Values()</a>, <a class="el" href="group__cresample__v4__0.html#gac15c402d317aea7dbcdabdae1c6d8e6c">XCresample_DisableDbgBypass()</a>, <a class="el" href="group__cresample__v4__0.html#ga1f6adeb2af84970d6d20a70be30169dd">XCresample_DisableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#ga930ea9583c5dd76de763fae86d6b1eff">XCresample_EnableDbgByPass()</a>, <a class="el" href="group__cresample__v4__0.html#ga32b603c19c2afaee47a70dde41fdcaa1">XCresample_EnableDbgTestPattern()</a>, <a class="el" href="group__cresample__v4__0.html#gaa92fd02ee15f7f102dde33a7b2d904d3">XCresample_SetActiveSize()</a>, <a class="el" href="group__cresample__v4__0.html#ga81bd9651d3634a4f93adc0c9aa377bd4">XCresample_SetChromaParity()</a>, and <a class="el" href="group__cresample__v4__0.html#gaf88e4da9bfb514e7f31550e4763b5ff1">XCresample_SetFieldParity()</a>.</p>

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